NoC support for dynamic FPGA pages

Module-based FPGA reconfiguration offers virtualization and multitasking capabilities, but to support this, many problems need to be solved. Current methodologies are very specific and are not capable of scaling or of being reused for other applications. This thesis proposes a methodology whereby the use of dynamic reconfiguration is supported for every core independent of the communication interface and communication needs. The infrastructure introduces a general interface for attaching and detaching dynamically reconfigurable modules and a Network on Chip (NoC) to provide communication between modules and off-chip resources. The approach advocates the regular layout of modules on the device, which are connected with a network, helping to generalize the interface and share the communication lines. The NoC provides essential advantages such as scalability, increased parallelism and simplifying the process of partial dynamic reconfiguration. The interface between NoC and reconfigured modules requires a glue logic. Guidelines were composed for designing a simple, working and reusable Network Interface core (NWIF) for a general types of cores. This allows to use the regular layout with the NoC as a communication medium for multitasking or virtualiziation, where the modules may be easily replaced. The results of implemented examples using the guidelines are presented. The performance compared to the conventional design is worse in the NoC design and the overhead is significant, but the reusability, generalism of the interface and the scalability of the framework are improved for future applications. Several avenues for improving the prototype developed in this work are exposed.